Implementation of an integrated circuit include one or more stages of processing on a logic which is to be implemented. For a FPGA device, the logic may initially be synthesised based on user inputs including one or more design constraints. Further, using the synthesized logic, implementation may be performed. One or more conventional methods are available to perform the implementation using an implementation tool or an implementation platform
In conventional methods for the implementation, include placing process and routing process on the logic. Along with the placing process and the routing process, post placement optimization and post routing optimization may be performed in the conventional methods. Each of post placement optimization and post routing optimization may include one or more processes such as, fan-out optimization process, re-routing process, register replication process, retiming process and so on. By the fan-out optimization process, load on driving nets of the logic may be reduced. By the re-routing process, re-routing with short length routes may be performed. By the register replication process, driving flops may be replicated to reduce load on each of the driving flops. By the re-timing process (adjusting of combinatorial logic between adjacent flip-flop stages may be performed. By said post placement optimization and said post routing optimization, only minor corrections associated with the placing and the routing may be performed. Hence, the post placement optimization and the post routing optimization may be effective only if there are few timing violations and the timing violations are negligible. Also, the post placement optimization and the post routing optimization may not be configured to perform gross corrections which include major changes in the placing based on the mapping and major changes in the routing based on the placing. In the present time, with enhancement in technology associated with integrated circuits and considering that the FPGA devices are developed with bigger size and higher capacity, the gross corrections may be essential to obtain an optimal timing performance of user logic in the FPGA device.
The information disclosed in this background of the disclosure section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.